EDN

Applying Constrained-Random Verification to Microprocessors

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification

UVM testbenches for blocks are adequate until the stage of a subsystem with one or more processors. The new generation of constrained-random test cases based on scenario models can take it from there.
Design-Reuse

Using Vera and Constrained-Random Verification to Improve DesignWare Core Quality

As more system-on-chip (SoC) engineers rely on re-use to cut design time and reduce risk, the demand for synthesizable cores and other forms of intellectual property (IP) continues to rise ...
Design-Reuse

Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Reference Verification Methodology (RVM)

Verification is one of the biggest challenges for System-on-Chip (SoC) designs, and traditional methods have run out of steam. Writing individual tests is impractical for today’s large, complex ...